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SpaceFibre on Microsemi RTG4

Microsemi RTG4 FPGA

The RTG4 FPGA is a new radiation tolerant FPGA from Microsemi which is fully reprogrammable and which has an integrated flash memory to store configuration information. The RTG4 architecture is illustrated in Figure 1. Microsemi RTG4 FPGA Architecture

Figure 1 Microsemi RTG4 FPGA Architecture

The RTG4 contains 151,824 logic elements each comprising a 4-input LUT and flip-flop capable of operating at a clock speed of 250 MHz. There are 209 blocks of dual-port SRAM which can each be configured as 512 x 36, 1 kbit x 18, 2 kbit x 9 or 2 kbit x 12 memory blocks. The RTG4 also includes 210 three-port SRAM blocks which can each be configured as 64 x 18, 128 x 12 or 128 x 9. To access external memory there are two high-speed DDR2/DDR3 memory controllers which can operate at 333MHz and support x9, x12, x18 and x36 bus widths. The memory controllers provide optional error detection and correction (EDAC) for the external memory devices. The RTG4 has 462 math blocks, each of which contains an 18x18-bit multiplier and a 44-bit accumulator. The math blocks can provide 250 MHz pipelined performance giving a total potential DSP performance of 230 GOPS. The math blocks are ideal for many DSP functions including filters and Fast Fourier Transforms (FFTs).

The RTG4 includes 24 high-speed (3.125 Gbits/s) serial interfaces integrated on-chip suitable for SpaceFibre. STAR-Dundee has already demonstrated SpaceFibre running over the RTG4. In addition the RTG4 has 16 SpaceWire clock and data recovery circuits, which support SpaceWire interfaces running at over 300 Mbits.

The 65nm flash process used in the RTG4 devices is intrinsically immune to configuration upsets, and the devices also feature additional radiation protection for data in flip-flops and combinatorial logic elements, embedded SRAM cells and multiply accumulate blocks. The RTG4 is designed to eliminate single-event latch-ups.

SpaceFibre on the RTG4 FPGA

To implement SpaceFibre a high-speed serialiser/de-serialiser (SerDes) is required, which takes relatively slow, parallel data and serialises it for transmission at high-speed and de-serialises the received serial data to recover the parallel data stream. In the past external SerDes devices have been used with FPGAs, such as the RTAX2000 from Microsemi, to provide a high-speed serial interface. STAR-Dundee has implemented SpaceFibre on such an FPGA using a separate SerDes chip, the TLK2711-SP from Texas Instruments.

The RTG4 FPGA includes radiation tolerant SerDes on-chip avoiding the need for external SerDes devices. These integrated SerDes make the RTG4 ideal for the implementation of spaceflight data-handling and processing sub-systems with multi-Gbits/s SpaceFibre interfaces.

SerDes Operation

The RTG4 FPGA contains 24 general purpose, high-speed serial/de-serialiser (SerDes) lanes. The block diagram of an RTG4 SerDes is provided in Figure 8.SerDes Detailed Block Diagram

Figure 2 SerDes Detailed Block Diagram

The data to be transmitted by the SerDes (TX Data) is passed in parallel words to the serialiser. The transmit clock for the serialiser is generated by a transmit phase-locked loop (PLL) which takes a reference clock and multiplies it up to give the required serial bit rate. The reference clock is at the same rate as the parallel words going into the serialiser. The serialiser takes each parallel word and converts it into a serial bit stream at the appropriate bit rate and passes it to a line transmitter which provides a current mode logic (CML) serial output.

The received serial data comes into the CML receiver and is passed to a deserialiser. A clock data recovery (CDR) circuit generates a clock signal from the received bit stream. This is then used to clock the deserialiser, which converts the serial input stream into parallel words. A signal detection circuit is used to detect when a receive signal is present on the input of the receiver. The inverse of this signal is used to provide the Loss of Signal indication required for SpaceFibre.

FPGA Resources Needed For SpaceFibre

The FPGA resources used to implement a SpaceFibre IP core in the RTG4 FPGA are listed in Table 1 and Table 2, depending on whether the Single-Lane or the Multiple-Lane IP is required and the number of Virtual Channels (VC). Additional information of the resource usage for other radiation tolerant FPGAs can be found in the SpaceFibre IP Core Datasheet. The number of flip-flops, look-up tables (LUTs) and RAM blocks used are detailed in the table, along with the percentage of those elements of the complete RTG4 device. In addition each SpaceFibre lane uses one of the inbuilt radiation tolerant SerDes elements of the RTG4.

Table 1 RTG4 Resource Usage for Single-Lane SpaceFibre IP

  LUT DFF RAM
Block
1 VC 3944
(2.6%)
2818
(1.9%)
4
(1.9%)
2 VC 4454
(2.9%)
3197
(2.1%)
6
(2.9%)


Table 2 RTG4 Resource Usage
 for Multi-Lane SpaceFibre IP

  LUT DFF RAM
Block

2 Lanes
1 VC

6494
(4.3%)
5351
(3.5%)
8
(3.8%)

2 Lanes
2 VC

7314
(4.8%)
6088
(4.0%)
12
(5.7%)

3 Lanes
2 VC

8997
(5.9%)
7413
(4.8%)
12
(5.7%)

A video demonstrating the operation of SpaceFibre can be found on the Microsemi partners page.