SpaceWire IP Cores

STAR-Dundee offers a comprehensive range of SpaceWire and SpaceFibre IP cores used across the space industry in flight FPGAs and ASICs.

Two independant IP cores are availible that together support the SpaceWire standard:

  • SpaceWire Interface IP
  • SpaceWire Router IP

Each of our SpaceWire IP cores has the following features:

  • Delivered as synthesisable VHDL source code in obfuscated or clear code format
  • Configurable, giving flexibility through generics in the VHDL source
  • Low power, carefully designed to minimise switching frequencies and with a number of features including automatic power-down/power-up as required
  • Easily targeted for major FPGAs including Microsemi, Xilinx, Intel and BRAVE. Support for radiation tolerant device features including the Microsemi RTAX, ProASIC(3/3E/3L and RTG4. Please contact STAR-Dundee for other target devices.
  • Reference designs are available for Microsemi ProASIC3L and RTG4 devices. Please contact STAR-Dundee for other target devices.

The SpaceWire IP Cores are designed to provide the user with high-performance, low power consumption SpaceWire capability at a lower cost than developing a core in house.These cores are present in STAR-Dundee’s test and development equipment and have been widely used across the space industry, including in the SpaceWire 10X Router ASIC (AT7910E) and SpaceWire Remote Terminal Controller ASIC (AT7913E) radiation tolerant chips available from Atmel.

Different licences and licence upgrade options are available to help users reduce their costs even further. Discounts may also be applied for Universities and ESA member states.

Further information on the SpaceWire IP Cores can be found in the datasheets below, and for technical queries please enter any questions in the additional comments section of the quotation (becomes available once you click Request Quote). Alternatively you may use the Quick Price Enquiry Form to ask any questions you have.

Product Features

  • Fully compliant to the SpaceWire Standard

  • Provided as VHDL code

  • Great control and flexibility through editing generics in VHDL

  • Low power consumption by design

  • Discounts available for single mission use, research, or ESA member states

  • SpaceWire Interface:

    • SpaceWire interface design
    • Data and time-code interfaces
    • Status and error reporting
    • Single or double data rate modes supported
    • Range of clocking options supported
  • SpaceWire Router:

    • SpaceWire Router with up to 31 ports, SpaceWire or external parallel FIFOs
    • Internal configuration port
    • Configuration performed with the RMAP protocol (ECSS-E-ST-50-52C)
    • Non-blocking crossbar switch
    • Time-code interface with additional Time-code master functionality
    • Default configuration compatible with SpW-10X ASIC (AT7910E) available from Atmel

Technical Specs

  • Available Cores
    • SpaceWire Interface

    • SpaceWire Router

  • Approx. utilisation estimates
    • SpaceWire Interface:

      • 463/385/2 (FF/COMB/RAM) sites in an RTAX1000/2000 device (pre EDAC memory core insertion)
      • 2100 tiles (3900 Synplify TMR enabled) in a ProASIC3L device with EDAC memory core insertion)
      • 380/520/3 (FF/LUT/RAM64x16) sites in an RTG4 150 device with EDAC protection enabled
      • 352/344/2 (FF/LUT/RAM) sites in a Virtex5QV device (pre EDAC memory core insertion)
      • Contact STAR-Dundee for specific utilisation figures for other target devices
    • SpaceWire Router:

      • 50% RTAX2000 (4 SpaceWire ports, 1 parallel FIFO port)
      • 6747/15496/24 (FF/LUT/RAM) sites in an RTG4 150 device, 11% utilisation, with EDAC protection enabled (14x ports, 12 SpW ports, 1 parallel FIFO port, pre address table scrubbing insertion)
      • Contact STAR-Dundee for specific utilisation figures for other target devices
  • Content
    • Supplied as VHDL code

  • Licencing options
    • Variety of licence and licence upgrade options available, any needs can be discussed with STAR-Dundee