SpaceFibre IP Cores
STAR-Dundee has developed a range of SpaceFibre IP cores which have already been designed into radiation-hardened FPGAs and ASICs. These IP cores provide the building blocks required for creating the next generation of onboard networks. The available IP cores are:
- SpaceFibre Single-Lane Interface – Speeds ranging from 1 to more than 6.25 Gbit/s
- SpaceFibre Multi-Lane Interface – Supports any number of lanes (up to 8 lanes, aggregate rates of up more than 50 Gbit/s)
- SpaceFibre Single-Lane Router – Number and types of ports is fully configurable (includes the possibility of configuring some ports as SpaceWire or Internal AXI4-Stream ports)
- SpaceFibre Multi-Lane Router – Same capabilities as the Single-Lane Router, and also allowing to configure the number of lanes of each SpaceFibre port.
The IP Cores are delivered with reference designs targeting different FPGA technologies. These designs provide a path for fast adoption in the selected FPGA technology, making it easy to become familiar with the use of the IP in a specific FPGA. This in turn helps to reduce the time and effort required to implement SpaceFibre in the final design.
STAR-Dundee SpaceFibre IP cores are supported in the following radiation-hardened/tolerant FPGA families:
- Microchip RTG4
- Microchip RT PolarFire
- Xilinx Kintex UltraScale
- Xilinx Versal
- NanoXplore BRAVE (available soon)
- Xilinx Virtex-5QV
- Microchip RTAX (Single-Lane Interface only)
Furthermore, support is also included for relevant commercial FPGAs including (but not limited to):
- Altera Arria 10 / Cyclone V (available soon)
- Microchip SmartFusion2
- Xilinx 7-series, Zynq, Zynq UltraScale+
The SpaceFibre IPs include support for external transceiver devices such as the TLK2711-SP.
If you require support for a technology not listed here or have any questions regarding the use of SpaceFibre IP cores with these technologies, please contact STAR-Dundee.
These cores are fully compliant to the ECSS-E-ST-50-11C SpaceFibre standard.
Further information on the SpaceFibre IP Cores can be found in the datasheets below, and for technical queries please enter any questions in the additional comments section of the quotation (this becomes available once you click Request Quote). Alternatively you may use the Quick Price Enquiry Form to ask any questions you may have.
Minimum implementation complexity:
- Simple data interfaces based on standard input and output FIFO interfaces (AXI4-Stream) with independent user-defined data read and write AXI clocks
- Easy to use with a protocol agnostic interface. No prior knowledge of SpaceFibre standard is required. The SpaceWire packet size, format and content is arbitrary
- Highly configurable, giving flexibility through generics in the VHDL source code
- Easily targeted for major FPGAs including radiation-hardened devices such as the Microchip RTG4 and Xilinx Virtex-5QV or Kintex UltraScale
- Status and error reporting
- Data and broadcast babbling-node protection
- Guaranteed timing closure in radiation-tolerant FPGAs with EDAC and SET filter enabled and worst-case conditions
- Supports lane rates up to 3.125 Gbit/s in RTG4 or Virtex-5QV, and 6.25 Gbit/s in Kintex UltraScale
- When Multi-Lane is used:
- Automatic graceful degradation
- Lanes can be configured as unidirectional to save power and mass in asymmetric data flows
- Hot and cold redundancy supported
- Possibility to start one end of the link in a low-power mode waiting for the other end to become active
- Optimised for low latency operation
Compliant with the ECSS-E-ST-50-11C SpaceFibre standard
Designed by the same team who created the standard