SpaceFibre IP Cores
STAR-Dundee has developed a range of SpaceFibre IP cores which have already been designed in to radiation-hardened FPGAs and ASICs. These IP cores provide all the building blocks necessary for creating the next generation of onboard networks. The available IP cores are:
- SpaceFibre Interface – Single-Lane, with speeds ranging from 1 Gbit/s to 6.25 Gbit/s
- SpaceFibre Interface – Multi-Lane, supporting any number of lanes between 2 and 8 (aggregate data rates of up to 50 Gbit/s)
Furthermore, additional SpaceFibre IP cores are currently in the final stages of development. They have already been demonstrated in FPGAs but have not yet been released as products. These include:
- SpaceFibre Router (includes the possibility of configuring some ports as SpaceWire)
- SpaceWire to SpaceFibre Bridge
For further information on any of these IP cores please contact STAR-Dundee.
The IP Cores are delivered with reference designs targeting different FPGA technologies. These designs provide a path for fast adoption in the selected FPGA technology, making it easy to become familiar with the use of the IP in a specific FPGA. This in turn helps to reduce the time and effort required to implement SpaceFibre in the final design.
STAR-Dundee SpaceFibre IP cores are supported in the following radiation-hardened/tolerant FPGA families:
- Microchip RTG4
- Xilinx Virtex-5QV
- Xilinx Kintex UltraScale
Furthermore, support is also included for relevant commercial FPGAs including (but not limited to):
- Microchip SmartFusion2
- Xilinx Virtex-5
- Xilinx Spartan-6
- Xilinx Artix-7, Kintex-7 & Virtex-7
- Xilinx Zynq UltraScale+
Work is ongoing to support the new radiation-hardened NanoXplore BRAVE family of FPGAs and commercial Altera devices. If you require support for a technology not listed here or have any questions regarding the use of SpaceFibre IP cores with these technologies, please contact STAR-Dundee.
These cores are fully compliant to the most recently published version of the SpaceFibre specification.
Further information on the SpaceFibre IP Cores can be found in the datasheets below, and for technical queries please enter any questions in the additional comments section of the quotation (this becomes available once you click Request Quote). Alternatively you may use the Quick Price Enquiry Form to ask any questions you may have.
Compliant with the SpaceFibre standard. Supports all the standard functionality
Designed by the same team who created the standard
Minimum implementation complexity
Optimised for low latency operation
Highly configurable, giving flexibility through generics in the VHDL source. The following characteristics can be configured:
- Loopback mode
- Number of Virtual Channels (up to 32)
- Size of the Virtual Channel buffers
- Size of the retry buffers
The Quality of Service parameters can be configured in real time during operation
Simple data and broadcast interfaces based on standard input and output FIFO interfaces
Possibility to start one end of the link in a low-power mode waiting for the other end to become active
Status and error reporting
Data and broadcast babbling idiot protection
Easily targeted for major FPGAs including radiation hard devices such as the Microsemi RTAX and RTG4